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rev. b a ad8016 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. low power, high output current xdsl line driver pin configuration features xdsl line driver that features full adsl co (central office) performance on 12 v supplies low power operation 5 v to 12 v voltage supply 12.5 ma/amp (typ) total supply current power reduced keep alive current of 4.5 ma/amp high output voltage and current drive i out = 600 ma 40 v p-p differential output voltage r l = 50 , v s = 12 v low single-tone distortion ?5 dbc @ 1 mhz sfdr, r l = 100 , v o = 2 v p-p mtpr = ?5 dbc, 26 khz to 1.1 mhz, z line = 100 , p line = 20.4 dbm high speed 78 mhz bandwidth (? db), g = +5 40 mhz gain flatness 1000 v/ s slew rates product description the ad8016 high output current dual amplifier is designed for the line drive interface in digital subscriber line systems such as adsl, hdsl2, and proprietary xdsl systems. the driv ers are capable, in full-bias operation, of providing 24.4 dbm output power into low resistance loads, enough to power a 20.4 dbm line, including hybrid insertion loss. frequency (khz) 549.3 10db/div 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3 ?5dbc figure 1. multitone power ratio; v s = 12 v, 20.4 dbm output power into 100 ? , downstream 24-lead batwing (rb-24) 20-lead psop3 (rp-20) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 + + ad8016 nc = no connect v out 1 +v1 +v2 v inn 1 v inp 1 nc nc nc pwdn0 dgnd ?1 v out 2 v inn 2 v inp 2 nc nc nc pwdn1 bias ?2 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 + + ad8016 nc = no connect +v1 +v2 v out 1 v inn 1 v inp 1 agnd agnd agnd agnd pwdn0 dgnd ?1 nc v out 2 v inn 2 v inp 2 agnd agnd agnd pwdn1 bias ?2 nc agnd 28-lead tssop-ep (re-28-1) nc nc nc bias ?2 +v1 +v2 v out 1 ? in 1 pwdn1 dgnd ?1 v out 2 +v in 2 pwdn0 nc = no connect nc nc nc ? in 2 +v in 1 nc nc nc nc nc nc nc nc 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad8016are the ad8016 is available in a low cost 24-lead so-batwing, a thermally enhanced 20-lead psop3, and a 28-lead tssop-ep with an exposed lead frame (epad). operating from 12 v sup plies, the ad8016 requires only 1.5 w of total power dissipation (refer to the power dissipation section for details) while driving 20.4 dbm of power downstream using the xdsl hybrid in figure 33a and figure 33b. two digital bits (pwdn0, pwdn1) allow the driver to be capable of full perfor- mance, an output keep-alive state, or two intermediate bias states. the keep-alive state biases the output transistors enough to provide a low impedance at the amplifier outputs for back termination. t he lo w power dissipation, high output c urrent, high output voltage swing, flexible power-down, and robust thermal packaging enable the ad8016 to be used as the central office (co) terminal driver in adsl, hdsl2, vdsl, and proprietary xdsl systems.
rev. b e2e ad8016especifications parameter conditions min typ max unit dynamic performance e3 db bandwidth g = +1, r f = 1.5 k , v out = 0.2 v p-p 380 mhz g = +5, r f = 499 , v out < 0.5 v p-p 69 78 mhz bandwidth for 0.1 db flatness g = +5, r f = 499 , v out = 0.2 v p-p 16 38 mhz large signal bandwidth v out = 4 v p-p 90 mhz peaking v out = 0.2 v p-p < 50 mhz 0.1 db slew rate v out = 4 v p-p, g = +2 1000 v/ s rise and fall time v out = 2 v p-p 2 ns settling time 0.1%, v out = 2 v p-p 23 ns input overdrive recovery time v out = 12.5 v p-p 350 ns noise/distortion performance distortion, single-ended v out = 2 v p-p, g = +5, r f = 499 second harmonic f c = 1 mhz, r l = 100 /25 e75/e62 e77/e64 dbc third harmonic f c = 1 mhz, r l = 100 /25 e88/e74 e93/e76 dbc multitone power ratio * 26 khz to 1.1 mhz, z line = 100 , p line = 20.4 dbm e75 dbc im d 500 khz, f = 10 khz, r l = 100 /25 e84/e80 e88/e85 dbc ip3 500 khz, r l = 100 /25 42/40 43/41 dbm voltage noise (rti) f = 10 khz 2.6 4.5 nv/ hz hz hz h h hz
rev. b e3e ad8016 parameter conditions min typ max unit dynamic performance e3 db bandwidth g = +1, r f = 1.5 k , v out = 0.2 v p-p 320 mhz g = +5, r f = 499 , v out < 0.5 v p-p 70 71 mhz bandwidth for 0.1 db flatness g = +5, r f = 499 , v out = 0.2 v p-p 10 15 mhz large signal bandwidth v out = 1 v rms 80 mhz peaking v out = 0.2 v p-p < 50 mhz 0.7 1.0 db slew rate v out = 4 v p-p, g = +2 300 v/ s rise and fall time v out = 2 v p-p 2 ns settling time 0.1%, v out = 2 v p-p 39 ns input overdrive recovery time v out = 6.5 v p-p 350 ns noise/distortion performance distortion, single-ended g = +5, v out = 2 v p-p, r f = 499 second harmonic f c = 1 mhz, r l = 100 /25 e73/61 e75/e63 dbc third harmonic f c = 1 mhz, r l = 100 /25 e80/e68 e82/e70 dbc multitone power ratio * 26 khz to 138 khz, z line = 100 , p line = 13 dbm e68 dbc im d 500 khz, f = 110 khz, r l = 100 /25 e87/e82 e88/e83 dbc ip3 500 khz 42/39 42/39 dbm voltage noise (rti) f = 10 khz 4 5 nv/ hz hz hz h h hz
rev. b ad8016 e4e absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 v internal power dissipation psop3 package 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 w so-batwing package 3 . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 w tssop-ep package 4 . . . . . . . . . . . . . . . . . . . . . . . . 1.4 w input voltage (common-mode) . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . v s output short-circuit duration . . . . . . . . . . . . . . . . . . . .o bserve power derating curves storage temperature range . . . . . . . . . . . . . e65 c to +125 c operating temperature range . . . . . . . . . . . . e40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device on a 4-layer board with 10 inches 2 of 1 oz. copper at 85 c 20-lead psop3 package: ja = 18 c/w. 3 specification is for device on a 4-layer board with 10 inches 2 of 1 oz. copper at 85 c 24-lead batwing package: ja = 28 c/w. 4 specification is for device on a 4-layer board with 9 inches 2 of 1 oz. copper at 85 c 28-lead (tssop-ep) package: ja = 29 c/w. maximum power dissipation the maximum power that can be safely dissipated by the ad 8016 is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsulated device is determined by the glass transition temperature of the plastic, approximately 150 c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. the output stage of the ad8016 is designed for maximum load current capability. as a result, shorting the output to common can cause the ad8016 to source or sink 2000 ma. to ensure proper operation, it is necessary to observe the maximum power derating curves. direct connection of the output to either power supply rail can destroy the device. ambient temperature ( c ) 7 0 maximum power dissipation (w) 6 5 4 3 2 1 0 10 20 30 40 50 60 70 80 90 psop3 so-batwing 8 tssop-ep figure 2. maximum power dissipation vs. temperature for ad8016 for t j = 125 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8016 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide temperature package package model range description option ad8016arp e40 c to +85 c 20-lead psop3 rp-20a ad8016arp-reel e40 c to +85 c 20-lead psop3 rp-20a ad8016arp-eval evaluation board ad8016arb e40 c to +85 c 24-lead so-batwing rb-24 ad8016arb-reel e40 c to +85 c 24-lead so-batwing rb-24 ad8016arb-eval evaluation board ad8016are e40 c to +85 c 28-lead tssop-ep re-28-1 ad8016are-reel e40 c to +85 c 28-lead tssop-ep re-28-1 ad8016are-reel7 e40 c to +85 c 28-lead tssop-ep re-28-1 ad8016are-eval evaluation board
rev. b ad8016 e5e t ypical performance characteristicse 0.1 f 0.1 f 10 f 10 f 49.9 124 499 r l v out +v s ev s + + v in figure 3. single-ended test circuit; g = +5 v out = 100mv v in = 20mv volts time (100ns/div) figure 4. 100 mv step response; g = +5, v s = 6 v, r l = 25 , single-ended v out = 5v v in = 800mv time (100ns/div) volts figure 5. 4 v step response; g = +5, v s = 6 v, r l = 25 , single-ended 499 49.9 +v in r l 499 111 49.9 ev in +v o ev o +v s ev s 0.1 f 10 f + 0.1 f 10 f + figure 6. differential test circuit; g = +10 v out = 100mv v in = 20mv volts time (100ns/div) fig ure 7. 100 mv step respon se; g = +5, v s = 12 v, r l = 25 , single-ended v out = 4v v in = 800mv volts time (100ns/div) figure 8. 4 v step response; g = +5, v s = 12 v, r l = 25 , single-ended
rev. b ad8016 e6e (0,1) (1,0) e30 0.01 10 1 0.1 e110 e100 e90 e80 e70 e60 e50 e40 20 r f = 499 g = +10 v o = 4v p-p (0,0) frequency (mhz) distortion (dbc) pwdn1, pwdn0 = (1,1) figure 10. distortion vs. frequency; second harmonic, v s = 6 v, r l = 50 , different (0,1) peak output current (ma) e30 0 100 distortion (dbc) 200 e80 e75 e70 e65 e60 e55 e50 e40 r f = 499 g = +5 (0,0) e35 e45 300 400 500 600 700 800 (1,0) pwdn1, pwdn0 = (1,1) figure 11. distortion vs. peak output current; second harmonic, v s = 12 v, r l = 10 , f = 100 khz, single-ended (1,0) (0,1) frequency (mhz) e30 0.01 10 distortion (dbc) 1 0.1 e110 e100 e90 e80 e70 e60 e50 e40 20 r f = 499 g = +10 v o = 4v p-p (0,0) pwdn1, pwdn0 = (1,1) figure 9. distortion vs. frequency; second harmonic, v s = 12 v, r l = 50 , differential (0,1) frequency (mhz) e30 0.01 10 distortion (dbc) 1 0.1 e110 e100 e90 e80 e70 e60 e50 e40 20 r f = 499 g = +10 v o = 4v p-p (0,0) (1,0) pwdn1, pwdn0 = (1,1) figure 12. distortion vs. frequency; third harmonic, v s = 12 v, r l = 50 , differential (1,0) (0,1) frequency (mhz) e30 0.01 10 distortion (dbc) 1 0.1 e110 e100 e90 e80 e70 e60 e50 e40 20 r f = 499 g = +10 v o = 4v p-p (0,0) pwdn1, pwdn0 = (1,1) figure 13. distortion vs. frequency; third harmonic, v s = 6 v, r l = 50 , differential (1,0) (0,1) peak output current (ma) e30 0 100 distortion (dbc) 200 e90 e80 e70 e50 r f = 499 g = +5 (0,0) e40 e60 300 400 500 600 700 pwdn1, pwdn0 = (1,1) figure 14. distortion vs. peak output current, third harmonic; v s = 12 v, r l = 10 , g = +5, f = 100 khz, single-ended
rev. b ad8016 e7e (1,0) (0,1) peak output current (ma) e30 0 100 distortion (dbc) 200 e80 e75 e70 e65 e60 e55 e50 e40 r f = 499 g = +5 (0,0) e35 e45 300 400 500 600 pwdn1, pwdn0 = (1,1) figure 15. distortion vs. peak output current; second harmonic, v s = 6 v, r l = 5 , f = 100 khz, single-ended (0,1) differential output (v p-p) e30 05 distortion (dbc) 10 e100 e90 e80 e70 e50 (0,0) e40 e60 15 20 25 30 35 40 (1,0) pwdn1, pwdn0 = (1,1) figure 16. distortion vs. output voltage; second harmonic, v s = 12 v, g = +10, f = 1 mhz, r l = 50 , differential (1,0) (0,1) differential output (v p-p) e30 05 distortion (dbc) 10 e90 e80 e70 e50 (0,0) e40 e60 15 20 pwdn1, pwdn0 = (1,1) figure 17. distortion vs. output voltage; second harmonic, v s = 6 v, g = +10, f = 1 mhz, r l = 50 , differential (1,0) (0,1) peak output current (ma) e30 0 100 distortion (dbc) 200 e80 e75 e70 e65 e60 e55 e50 e40 (0,0) e35 e45 300 400 500 600 pwdn1, pwdn0 = (1,1) figure 18. distortion vs. peak output current; third harmonic, v s = 6 v, g = +5, r l = 5 , f = 100 khz, single-ended (1,0) (0,1) differential output (v p-p) e30 05 distortion (dbc) 10 e100 e90 e80 e70 e50 (0,0) e40 e60 15 20 25 30 35 40 pwdn1, pwdn0 = (1,1) figure 19. distortion vs. output voltage; third harmonic, v s = 12 v, g = +10, f = 1 mhz, r l = 50 , differential (1,0) (0,1) differential output (v p-p) e30 05 distortion (dbc) 10 e90 e80 e70 e50 (0,0) e40 e60 15 20 pwdn1, pwdn0 = (1,1) figure 20. distortion vs. output voltage, third harmonic, v s = 6 v, g = +10, f = 1 mhz, r l = 50 , differential
rev. b ad8016 e8e frequency ( mhz ) 110 100 500 3 0 e3 e6 e9 e12 e15 e18 e21 e24 e27 normalized frequency response (db) v in = 40mv p-p g = +5 r l = 100 1,1 1,0 0,1 0,0 figure 21. frequency response; v s = 12 v, @ pwdn1, pwdn0 codes frequency ( mhz ) 1 output voltage (dbv) e16 e19 10 100 500 g = +5 r l = 100 r f = 499 e13 e10 e7 e4 e1 2 5 8 11 figure 22. output voltage vs. frequency; v s = 12 v frequency (mhz) 20 0.03 cmrr (db) 0.1 1 10 100 500 10 0 e10 e20 e30 e40 e50 e60 e70 e80 v in = 2v rms r f = 602 1,1 1,0 0,1 0,0 figure 23. cmrr vs. frequency; v s = 12 v @ pwdn1, pwdn0 codes frequency ( mhz ) 110 100 500 3 0 e3 e6 e9 e12 e15 e18 e21 e24 6 normalized frequency response (db) v in = 40mv p-p g = +5 r l = 100 1,1 0,1 1,0 0,0 figure 24. frequency response; v s = 6 v, @ pwdn1, pwdn0 codes frequency (mhz) 1 output voltage (dbv) e16 e19 10 100 500 e13 e10 e7 e4 e1 2 5 8 11 g = +5 r l = 100 r f = 499 figure 25. output voltage vs. frequency; v s = 6 v frequency ( mhz ) e10 0.01 psrr (db) e20 e30 e40 e50 e60 e70 e80 e90 0.1 1 10 100 500 +psrr epsrr r f = 499 figure 26. psrr vs. frequency; v s = 12 v
rev. b ad8016 e9e 0 frequency (mhz) 10 input voltage noise ( nv/ hz ) 100 80 60 40 20 100 1k 10k 10m 10 20 30 40 50 60 70 80 90 + input current noise (pa/ hz) 0 120 140 160 180 100k 1m +i noise v in noise figure 27. noise vs. frequency +2mv (e0.1%) e2mv (e0.1%) 0 0510 15 20 25 30 35 40 45 e5 g = +2 r f = 1k v out = 2v step r l = 100 output voltage error (2mv/div (0.1%/div)) v in v out time (ns) v out ev in figure 28. settling time 0.1%; v s = 12 v frequency ( mhz ) e30 0.03 crosstalk (db) 0.1 1 10 100 500 e40 e50 e60 e70 e80 e90 v out = 2v p-p r f = 499 g = +5 r l = 100 e20 figure 29. output crosstalk vs. frequency frequency (mhz) 10m 0.0001 transimpedance (k ) 100k 10k 1k 100 10 1 0.1 0.01 0 0.001 0.01 0.1 1 10 100 1000 10000 0 40 80 120 160 200 240 280 320 360 phase (degrees) transimpedance phase figure 30. open-loop transimpedance and phase vs. frequency 0510 15 20 25 30 35 40 45 e5 g = +2 r f = 1k v out = 2v step r l = 100 output voltage error (2mv/div (0.1%/div)) time (ns) +2mv (e0.1%) e2mv (e0.1%) 0 v out v in v out ev in figure 31. settling time 0.1%; v s = 6 v frequency (mhz) 1000 0.03 output impedance ( ) 0.1 1 10 100 500 100 10 1 0.1 0.01 0,0 0,1 1,1 1,0 figure 32. output impedance vs. frequency @ pwdn1, pwdn0 codes
rev. b ad8016 e10e v in = 2v/div v out = 5v/div v in v out e100 0 100 200 300 400 500 600 700 800 900 time (ns) 0v 0v figure 33a. overload recovery; v s = 12 v, g = +5, r l = 100 e100 0 100 200 300 400 500 600 700 800 900 time (ns) v in v out 0v 0v v in = 2v/div v out = 5v/div figure 33b. overload recovery; v s = 12 v, g = +5, r l = 100 i bias ( a) 25 0 i q (ma) 20 15 10 5 0 50 100 150 200 [0,1] [0,0] [1,0] pwdn1, pwdn0 = (1,1) figure 34. i q vs. i bias current; v s = 12 v i bias ( a) 18 0 i q (ma) 16 14 12 10 8 50 100 150 200 6 4 2 0 [1,0] [0,1] [0,0] pwdn1, pwdn0 = (1,1) figure 35. i q vs. i bias current; v s = 6 v r load ( ) output swing (v) 12 8 10 100 1k 10k 4 0 e4 e8 e12 +v out , v s = 12v +v out , v s = 6v ev out , v s = 6v ev out , v s = 12v figure 36. output voltage vs. r load
rev. b ad8016 e11e feedback resistor selection in current feedback amplifiers, selection of feedback and gain resistors has an impact on the mtpr performance, bandwidth, and gain flatness. care should be taken in selecting these resis- tors so that optimum performance is achieved. the table below shows the recommended resistor values for use in a variety of gain settings. these values are suggested as a good starting point when designing for any application. table i. resistor selection guide gain r f ( )r g ( ) +1 1000 e1 500 500 +2 650 650 +5 750 187 +10 1000 111 bias pin and pwdn features the ad8016 is designed to cover both co (central office) and cpe (customer premise equipment) ends of an xdsl applica- tion. it offers full versatility in setting quiescent bias levels for the particular application from full on to reduced bias (in three s teps) to full off (via bias pin). this versatility gives the modem designer the flexibility to maximize efficiency while maintaining reasonable levels of multitone power ratio (mtpr) performance. o ptimizing driver efficiency while delivering the required dmt power is accomplished with the ad8016 through the use of on-chip power management features. two digitally programmable logic pins, pwdn1 and pwdn0, may be used to select four different bias levels: 100%, 60%, 40%, and 25% of full quiescent power (see table ii). table ii. pwdn code selection guide pwdn1 pwdn0 code code quiescent bias level 11 100% (full on) 10 60% 01 40% 00 25% (low z out but not off) xx full off (high z out via 250 a pulled out of bias pin) the bias level can be controlled with ttl logic levels (high = 1) applied to the pwdn1 and pwdn0 pins alone or in combina- tion with the bias control pin. the dgnd or digital ground pin is the logic ground reference for the pwdn1 and pwdn0 pins. in typical adsl applications where 12 v or 6 v supplies (also single supplies) are used, the dgnd pin is connected to analog ground. the bias control pin by itself is a means to continuously adjust the ad8016 internal biasing and thus quiescent current i q . by pulling out a current of 0 a (or open) to approximately 200 a, the quiescent current can be adjusted from 100% (full on) to a full off condition. the full off condition yields a high output impedance. because of an on-chip resistor variation of up to 20%, the actual amount of current required to fully shut down the ad8016 can vary. to institute a full chip shutdown, a pull- down current of 250 a is recommended. see figure 38 for the logic drive circuit for complete amplifier shutdown. figures 34 and 35 show the relationship between current pulled out of the theory of operation t he ad8016 is a current feedback amplifier with high (500 ma) output current capability. with a current feedback amplifier, the current into the inverting input is the feedback signal and the open-loop behavior is that of a transimpedance, dv o /di in or t z . the open-loop transimpedance is analogous to the open-loop voltage gain of a voltage feedback amplifier. figure 37 shows a simplified model of a current feedback amplifier. since r in is proportional to 1/g m , the equivalent voltage gain is just t z g m , w here g m is the transconductance of the input stage. basic analysis of the follower with gain circuit yields v v g ts ts g r r o in z zinf = + + () () where: g r r r g f g in m =+ = 1 1 25 recognizing that g r in << r f for low gains, the familiar result of constant bandwidth with gain for current feedback amplifiers is evident, the 3 db point being set when |t z | = r f . of course, for a real amplifier there are additional poles that contribute excess phase and there is a value for r f below w hich the amplifier is unstable. tolerance for peaking and desired flatness determines the o ptimum r f in each application. t z r in i in + + e r f v out r n r g v in figure 37. simplified block diagram the ad8016 is the first current feedback amplifier capable of delivering 400 ma of output current while swinging to within 2v of either power supply rail. this enables full co adsl performance on only 12 v rails, an immediate 20% power saving. the ad8016 is also unique in that it has a power management system included on-chip. it features four user programmable pow er le vels (all of which provide a low output impedance of the driver), as w ell as the provision for complete shutdown (high impedance state). also featured is a thermal shutdown with alarm signal. power supply and decoupling the ad8016 should be powered with a good quality (i.e., low noise) dual supply of 12 v for the best distortion and multitone power ratio (mtpr) performance. careful attention must be paid to decoupling the power supply pins. a 10 f capacitor located in near proximity to the ad8016 is required to pro- vide good decoupling for lower frequency signals. in addition, 0.1 f decoupling capacitors should be located as close to each of the four power supply pins as is physically possible. all ground pins should be connected to a common low imped- ance ground plane.
rev. b ad8016 e12e bias pin (i bias ) and the supply current (i q ). a typical shut- down i q is less than 1 ma total. alternatively, an external pull- down resistor to ground or a current sink attached to the bias pin can be used to set i q to lower levels (see figure 39). the bias pin may be used in combination with the pwdn1 and pwdn0 pins; however, diminished mtpr performance may result when i q is lowered too much. current pulled away from the bias pin shunts away a portion of the internal bias current. setting pwdn1 or pwdn0 to logic 0 also shunts away a portion of the internal bias current. the reduction of quiescent bias levels due to the use of pwdn1 and pwdn0 is consistent with the percentages established in table ii. when pwdn0 alone is set to logic 0, and no other means of reducing the internal bias currents is used, full-rate adsl signals may be driven w hile maintaining reasonable levels of mtpr. r2 50k bias r1 * 3.3v logic 2n3904 * r1 = 47k for 12v s or +12v s , r1 = 22k for 6v s . figure 38. logic drive of bias pin for complete amplifier shutdown thermal shutdown the ad8016arb and ad8016arp have been designed to incorporate shutdown protection against accidental thermal overload. in the event of thermal overload, the ad8016 was designed to shut down at a junction temperature of 165 c and return to normal operation at a junction temperature 140 c. the ad8016 continues to operate, cycling on and off, as long as the thermal overload condition remains. the frequency of the protection cycle depends on the ambient environment, severity of the thermal overload condition, the power being dissipated, and the thermal mass of the pcb beneath the ad8016. when the ad8016 begins to cycle due to thermal stress, the internal shutdown circuitry draws current out of the node connected in common with the bias pin, while the voltage at the bias pin goes to the negative rail. when the junction temperature returns to 140 c, current is no longer drawn from this node, and the bias pin voltage returns to the positive rail. under these cir- cumstances, the bias pin can be used to trip an alarm indicat- ing the presence of a thermal overload condition. figure 39 also shows three circuits for converting this signal to a standard logic level. v cc 5v bias 10k alarm 1/4 hcf 40109b sgsethomson 10k 5v 100k 1m bias alarm min 350 or v ee 10k 200 a v cc bias pwdn1 bias or 0 ae200 a v = v cc e 0.2v shut- down ad8016 pwdn0 figure 39. shutdown and alarm circuit applications t he ad8016arp and ad8016arb dual xdsl line d river amplifiers are the most efficient xdsl line drivers available on the market today. the ad8016 may be applied in driving modu- la ted signals including discrete multitone (dmt) in either direction; upstream from cpe to the co and downstream from co to cp e. t he most significant thermal management chal- lenge lies in driving downstream information from co sites to the cpe. d riving xdsl information downstream sugg ests the need to locate many xdsl modems in a single co site. the implication is that several modems will be placed onto a single printed circuit board residing in a card cage located in a variety of ambient conditions. environmental conditioners such as fans or air conditioning may or may not be available, depending on the density of modems and the facilities contained at the co site. to achieve long-term reliability and consistent modem perfor- mance, designers of co solutions must consider the wide array of ambient conditions that exist within various co sites. multitone power ratio or mtpr adsl systems rely on discrete multitone modula tion to carry digital data over phone lines. dmt modulation appears in the frequency domain as power contained in several individual frequency subbands, sometimes referred to as tones or bins, each of which is uniformly separated in frequency. (see f igure 1 for an example of downstream dmt signals used in evaluating mtpr performance.) a uniquely encoded, quadrature amplitude m odu lation (qam) signal occurs at the center frequency of each subband or tone. difficulties arise when decoding these subbands if a qam signal from one subband is corrupted by the qam signal(s) from other subbands, regardless of w hether the corruption comes from an adjacent subband or harmonics of other subbands. conventional methods of expressing the output signal integrity of line drivers, such as spurious-free dynamic range (sfdr), single-tone harmonic distortion or thd, two-tone intermodulation distortion (imd), and third- order intercept (ip3) become significantly less meaningful when amplifiers are required to drive dmt and other heavily m odulated waveforms. a typical xdsl downstream dmt signal may contain as many as 256 carriers (subbands or tones) of qam signals. mtpr is the relative difference between the mea- sured power in a typical subband (at one tone or carrier) versus the power at another subband specifically selected to contain no qam data. in other words, a selected subband (or tone) remains open or void of intentional power (without a qam signal), yielding an e mpty frequency bin. mtpr, some- times referred to as t he empt y bin test, is typically expressed in dbc, similar to expressing the relative difference between single-tone fundamentals and second or third harmonic dis- tortion components. see figure 1 for a sample of the adsl downstream spectrum showing mtpr results while driving 20.4 dbm of power onto a 100 line. measurements of mtpr are typically made at the output (line side) of adsl hybrid circuits. (see figure 46a for an example of analog devices? hybrid schematic.) mtpr can be affected by the components contained in the hybrid circuit, including the quality of the capacitor dielectrics, voltage ratings, and the turns ratio of the selected transformers. other c ompo- nents aside, an adsl driver hybrid containing the ad8016 can be optimized for the best mtpr performance by selecting the turns ratio of the transformers. the voltage and current demands from the dif ferential driver changes, depending on the transformer
rev. b ad8016 e13e t urns ratio. the point on the curve indicating maximum dynamic headroom is achieved when the differential driver delivers both the maximum voltage and current while maintaining the lowest possible distortion. below this point, the driver has reserve current-driving capability and experien ces voltage clipping. above this point, the amplifier runs out of current drive capabil- ity before the maximum voltage drive capability is reached. since a transformer reflects the secondary load impedance back to the primary side by the square of the turns ratio, varying the turns ratio changes the load across the differential driver. in the transformer configuration of figure 46a and 46b, the turns ratio of the selected transformer is effectively doubled due to the parallel wiring of the transformer primaries within this adsl driver hybrid. the following equation may be used to calculate the load impedance across the output of the differential driver, refl ected by the transformers, from the line side of the xdsl driver hybrid. z' is the primary side impedance as seen by the differential driver; z 2 is the line impedance and n is the trans- former turns ratio. z z n ' () 2 2 2 figure 40 shows the dynamic headroom in each subband of a downstream dmt waveform versus turns ratio running at 100% and 60% of the quiescent power while maintaining e65 dbc of mtpr at v s = 12 v. 4 1.0 3 2 1.2 1.4 2.0 1 0 e1 1.6 1.8 e2 1.1 1.3 1.5 1.7 1.9 downstream turns ratio dynamic headroom (db) v s = 12v pwdn1, pwdn0 = (1,1) v s = 11.4v pwdn1, pwdn0 = (1,1) v s = 11.4v pwdn1, pwdn0 = (1,0) v s = 12v pwdn1, pwdn0 = (1,0) figure 40. dynamic headroom vs. xfmr turns ratio, v s = 12 v once an optimum turns ratio is determined, the amplifier has an mtpr performance for each setting of the power-down pins. the table below demonstrates the effects of reducing the total power dissipated by using the pwdn pins on mtpr perfor- mance when driving 20.4 dbm downstream onto the line with a transformer turns ratio of 1:1.4. table iii. dynamic power dissipation for downstream transmission pwdn1 pwdn0 pd (w) mtpr 11 1.454 e78 dbc 10 1.262 e75.3 dbc 01 1.142 e57.2 dbc 0 * 0 0.120 n/a * this mode is quiescent power dissipation. generating dmt at this time, dmt modulated waveforms are not typically menu- selectable items contained within arbitrary waveform generators. even using awg software to generate dmt signals, awgs that are available today may not deliver dmt signals sufficient in performance with regard to mtpr due to limitations in the d/a converters and output drivers used by awg manufacturers. similar to evaluating single-tone distortion performance of an amplifier, mtpr evaluation requires a dmt signal generator capable of delivering mtpr performance better than that of the driver under evaluation. generating dmt signals can be accom- plished using a tektronics awg 2021 equipped with opt 4, (12/24-bit, ttl digital data out), digitally coupled to analog devices ad9754, a 14-bit txdac , buffered by an ad8002 amplifier configured as a differential driver. see figure 45 for schematics of a circuit used to generate dmt signals that can achieve down to e80 dbc of mtpr performance, sufficient for use in evaluating xdsl drivers. note that the dmt waveforms available with the ad8016arp-eval and ad8016arb-eval boards or similar wfm files are needed to produce the neces- sary digital data required to drive the txdac from the optional ttl digital data output of the tek awg2021. copies of these wfm files can be obtained through the analog devices website, at www.analog.com. evaluation boards the ad8016arp-eval, ad8016arb-eval, ad8016are- eval boards available through analog devices provide a platform for evaluating the ad8016 in an adsl differential line driver circuit. the board is laid out to accommodate analog devices? two transformer line driver hybrid circuits (see figures 46a and 46b) including line matching network, an rj11 jack for interfacing to line simulators, transformer coupled input for single-to-differential input conversion, and accommodations for the receiver function. schematics and layout information are available for both versions of the evaluation board. also included in the package are wfm files for use in generating 14-bit dmt waveforms. upstream data is contained in the ...24.wfm files and downstream data in the ...128.wfm files. these dmt modulated signals are used to evaluate xdsl products for multitone power ratio or mtpr performance. the data files are used in pairs (adslu24.wfm and adsll24.wfm go together, etc.) and are loaded into a tek awg2021 arbi- trary waveform generator. the adslu24.wfm is loaded via the tek awg2021 floppy drive into channel 1, while the adsll24.wfm is simultaneously loaded into channel 2. the num- ber in the file name, prefixed with u, goes into ch1 or upper channel and the l goes into ch2 or the lower channel. 12 bits from ch1 are combined with 2 bits from ch2 to achieve 14-bit digital data at the digital outputs of the tek awg2021. the resulting waveforms produced at the ad9754-eb outputs are then buffered and amplified by the ad8002 differential driver to a chieve 14-bit performance from this dmt signal source. power dissipation in order to properly size the heat sinking area for the user?s application, it is important to consider the total power dissipa- tion of the ad8016. the dc power dissipation for v in = 0 is i q (v cc e v ee ), or 2 i q v s . for the ad8016 powered on +12 v and e12 v supplies ( v s ), the number is 0.6 w. in a differential driver circuit (figure 6),
rev. b ad8016 e14e one can use symmetry to simplify the computation for a dc input signal. pivvv v r dqs so o l = + 24(e) where: v o is the peak output voltage of an amplifier. this formula is slightly pessimistic due to the fact that some of the quiescent supply current is commutated during sourcing or sinking current into the load. for a sine wave source, integration over a half cycle yields piv vv r v r dqs os l o l = + ?

22 4 2 the situation is more complicated with a complex modulated signal. in the case of a dmt signal, taking the equivalent sine wave power overestimates the power dissipation by ~23%. for example: p out = 23.4 dbm = 220 mw v out @ 50 = 3.31 v rms v o = 2.354 v at each amplifier output, which yields a p d of 1.81 w. through measurement, a dmt signal of 23.4 dbm requires 1.47 w of power to be dissipated by the ad8016. figure 41 shows the results of calculation and actual measurements detail ing the relationship between the power dissipated by the ad8016 versus the total output power delivered to the back termination resistors and the load combined. a 1:2 transf ormer turns ratio was used in the calculations and measurements. output power (mw) 2.5 0 power dissipation 2.0 1.5 100 200 300 1.0 0.5 0 measured sine measured dmt calculated figure 41. power dissipation vs. output power (including back terminations), see figure 7 for test circuit thermal enhancements and pcb layout there are several ways to enhance the thermal capacity of the co solution. additional thermal capacity can be created using enhanced pcb layout techniques such as interlacing (sometimes referred to as stitching or interconnection) of the layers immedi- ately beneath the line driver. this technique serves to increase the thermal mass or capacity of the pcb immediately beneath the driver. (see ad8016-eval boards for an example of this method of thermal enhancement.) a cooling fan that draws moving air over the pcb and xdsl drivers, while not always required, may be useful in reducing the operating temperature of the die, allowing more drive within the co design. the ad8016, whether in a psop3 (arp) or so-batwing (arb) package, can be designed to operate in the co solution using prudent measures to manage the power dissipation through careful pcb design. the psop3 package is available for use in design- ing the highest density co solutions. maximum heat transfer to the pcb can be accomplished using the psop3 package when the thermal slug is soldered to an exposed copper pad directly beneath the ad8016. optimum thermal performance can be achieved in the are package only when the back of the package is soldered to a pcb designed for maximum thermal capacity (see figure 44). thermal experiments with the ps0p3 package were conducted without soldering the heat slug to the pcb. heat transfer was through physical contact only. the following offers some insight into the ad8016 power dissipation and relative junction temperature, as well as the effects of pcb size and composition on the junction-to-air thermal resistance or ja . thermal testing a wind tunnel study was conducted to determine the relation ship between thermal capacity (i.e., printed circuit board copper area), air flow, and junction temperature. junction-to-ambient ther- mal resistance, ja , was also calculated for the ad8016arp, ad8016are, and ad8016arb packages. the ad8016 was operated in a noninverting differential driver configuration, typical of an xdsl application yet isolated from any other modem components. testing was conducted using a 1 oz. copper board in an ambient temperature of ~24 c over air flows of 200, 150, 100, and 50 (0.200 and 400 for ad8016are) linear feet per minute (lfm) and for arp and arb packages as well as in still air. the 4-layer pcb was designed to maximize the area of copper on the outer two layers of the board, while the inner layers were used to configure the ad8016 in a differential driver circuit. the pcb measured 3 inches 4 inches in the beginning of the study and was progressively reduced in size to approxi mately 2 2 inches. the testing was performed in a wind tun nel to control air flow in units of lfm. the tunnel is approximately 11 inches in diameter. air flow test conditions dut power: typical dsl dmt signal produces about 1.5 w of power dissipation in the ad8016 package. the fully biased (pwdn0 and pwdn1 = logic 1) quiescent current of the ad8016 is ~25 ma. a 1 mhz differential sine wave at an amplitude of 8 v p-p/amplifier into an r load of 100 differential (50 per side) produces the 1.5 w of power typical in the ad 8016 device. (see the power dissipation section for details.) thermal resistance: t he jun ction-to-case thermal resistance ( jc ) of the ad8016arb or so-batwing package is 8.6 c/w, for the ad8016are or tssop-ep it is 5.6 c/w, and for the ad8016arp or psop3 package it is 0.86 c/w. these package specifications were used in this study to determine junction temperature based on the measured case temperature. pcb dimensions of a differential driver circuit: several components are required to support the ad8016 in a differential driver circuit. the pcb area necessary for these components (i.e., feedback and gain resistors, ac-coupling and decoupling capaci- t ors, termination and load resistors) dictated the area of the smallest pcb in this study, 4.7 square inches. further reduction in pcb area, although possible, has consequences in terms of the maximum operating junction temperature.
rev. b ad8016 e15e experimental results the experimental data suggests that for both packages, and a pcb as small as 4.7 square inches, reasonable junction tempera- tures can be maintained even in the absence of air flow. the graph in figure 42 shows junction temperature versus air flow for various dimensions of 1 oz. copper pcbs at an ambient temperature of 24 c in both the arb and arp packages. for the worst-case package, the ad8016arb and the worst-case pcb at 4.7 square inches, the extrapolated junction temperature for an ambient environment of 85 c would be approximately 132 c with 0 lfm of air flow. if the target maximum junction temperature of the ad8016arb is 125 c, a 4-layer pcb with 1 oz. cop per covering th e outer layers and measuring 9 square inches is required with 0 lfm of air flow. note that the ad8016are is targeted at xdsl applications other than full-rate co adsl. the ad8016are is targeted at g.lite and other xdsl applications where reduced power dissi- pation can be achieved through a reduction in output power. extreme temperatures associated with full-rate adsl using the ad8016are should be avoided whenever possible. air flow (lfm) 75 0 junction temperature ( c) 70 65 60 55 50 45 40 50 100 150 200 arp 6 sq-in arp 4.7 sq-in arp 12 sq-in arb 4.7 sq-in arb 7.125 sq-in arb 9 sq-in arb 6 sq-in arp 9 sq-in +24 c ambient figure 42. junction temperature vs. air flow pcb area (sq-in) 35 4 ja ( c/w) 30 25 20 15 10 710 arb 0 lfm arb 50 lfm arb 100 lfm arb 200 lfm arb 150 lfm arp 0 lfm arp 100 lfm arp 200 lfm arp 150 lfm arp 50 lfm figure 43. junction-to-ambient thermal resistance vs. pcb area 40 0 35 30 24 10 25 20 15 68 10 13579 50 45 pcb area (sq-in) ja ( c/w) are 0 lfm are 200 lfm are 400 lfm figure 44. junction-to-ambient thermal resistance vs. pcb area
rev. b ad8016 e16e figure 45. dmt signal generator schematic 10 9 8 765432 1 r4 10 9 8 7 6 5 4 3 2 1 r7 dvdd 10 9 8 7 6 5 4 3 2 1 r3 10 9 8 765432 1 dvdd r6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 p1 10 9 8 7 6 5 4 3 2 1 r5 dvdd 10 9 8 7 6 5 4 3 2 1 r1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c19 c1 c2 c25 c26 c27 c28 c29 16 pindip res pk 16 15 14 13 12 11 10 1 2 3 4 5 6 7 c30 c31 c32 c33 c34 c35 c36 16 pindip res pk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 clock dvdd dcom nc avdd comp2 i outa acom comp1 fs adj refio reflo sleep u1 ad9754 i outb avdd ct1 a 1 a r15 49.9 clk jp1 ab 3 2 1 j1 tp1 extclk c7 1 f c8 0.1 f avdd a c9 0.1 f tp8 2 avdd tp11 c11 0.1 f tp10 tp9 r16 2k tp14 jp4 c10 0.1 f out1 out2 tp13 r17 49.9 pdin j2 a a a avdd 3 jp2 tp12 tp7 a c6 10 f avcc b6 tp6 a c5 10 f avee b5 tp19 a agnd b4 tp18 tp5 c4 10 f tp4 avdd b3 tp2 dgnd b2 c3 10 f tp3 dvdd b1 j3 c12 22pf a j4 c13 22pf 98765432 1 r2 10 10 9 8 765432 1 dvdd r8 out2 out1 a r 20k 49.9 a 49.9 a 10k a 10k a 1 f 1 f ad8002 a avcc 249 a 0.1 f ad8002 a avee a 0.1 f 226 750 750 249 differential dmt outputs to tek awg 2021
rev. b ad8016 e17e p4 3 ad8016 14 22 21 u1 +v +vt evt ad8016 1 4 3 11 2 nc = 5, 6 agnd3,4,5 s5 tp10 tp5 c8 r11 r13 a b jp6 1 2 3 r24 r25 r23 1 2 3 6 4 t3 nc = 5 1:1 jp5 r15 r16 tp11 agnd3,4,5 s6 s3 s4 tp17 tp18 ad8022 ad8022 5 6 7 +vr;8 evr ; 4 +vr;8 evr;4 2 3 1 r1 5 watt 1 2 r17 tp6 tp7 c11 r20 pr1 pr2 1 2 3 4 t2 10 8 9 7 tp13 tp14 tp1 c4 c5 r2 c6 c7 tp15 tp16 r4 c9 p1 1 2 3 4 5 6 78 tp2 r5 tp8 p4 1 p4 2 nc = 5, 6 1 2 3 4 t1 10 8 9 7 r3 tp9 c12 r21 r18 r19 +v ev u1 +vt evt 24 23 ev r9 r6 u2 r7 u2 r14 tp4 c10 p3 1 p3 3 p3 2 figure 46a. schematic ad8016arb-eval s2 r10 p2 p2 p2 1 2 3 tp3 +vl r22 r12 jp1 jp2 r9 cw 15 10 9 16 5 6 7 8 17 18 u1 ad8016 bias dgnd pwdn0 pwdn1 agnd 19 20 agnd agnd agnd agnd agnd agnd agnd 13 12 nc + + tp19 tb1 3 tb1 2 tb1 1 l5 bead l1 bead c14 10 f 25v c1 10 f 25v c17 0.1 f c15 0.1 f c26 0.1 f c19 0.1 f c16 0.1 f c25 0.1 f tp20 +vt evt + + tb2 2 tb2 3 tb2 1 l4 bead l3 bead c13 10 f 25v c3 10 f 25v c21 0.1 f c23 0.1 f c24 0.1 f c22 0.1 f tp21 tp22 +vr evr + tb3 1 tb3 2 l2 bead c2 10 f 25v c20 0.1 f c18 0.1 f tp12 +vl +vt +vr jp3 evt evr jp4 tp24 tp23 tp25 tp26 tp27 tp28 tp29 tp30 nc figure 46b. schematic ad8016arb-eval
rev. b ad8016 e18e layout ad8016arb-eval figure 47. assembly figure 48. layer 1 figure 49. power/ground plane figure 50. layer 1 figure 51. silkscreen bottom
rev. b ad8016 e19e alp e evaluation board e bill of materials quantity description vendor ref desc. 5 10 f 25 v size tantalum chip capacitor ads# 4-7-2 c1 to c3, c13, c14 10 0.1 f 50 v 1206 size ceramic chip capacitor ads# 4-5-18 c15 to c21, c24 to c26 2 49.9 1% 1/8 w 1206 size chip resistor ads# 3-14-26 r11, r15 2 100 1% 1/8 w 1206 size chip resistor ads# 3-18-40 r8, r14 1 100 5% 3.0 w metal film power resistor ads# 3-24-1 r1 3 1.00 k 1% 1/6 w 1206 size chip resistor ads# 3-18-11 r17 to r19 2 10.0 k 1% 1/6 w 1206 size chip resistor ads# 3-18-119 r13 and r16 1 test point (black) [gnd] ads# 12-18-44 gnd 2 test point (brown) ads# 12-18-59 tp10, tp11 4 test point (red) ads# 12-18-43 tp17 to tp19, tp21 2 test point (orange) ads# 12-18-60 tp3, tp15, tp16 1 test point (yellow) ads# 12-18-32 tp12 2 test point (green) ads# 12-18-61 tp7, tp9 2 test point (blue) ads# 12-18-62 tp20, tp22 2 test point (violet) ads# 12-18-63 tp4, tp5 4 test point (grey) ads# 12-18-64 tp1, tp2, tp13, tp14 2 test point (white) ads# 12-18-42 tp6, tp8 23 green terminal block. onshore# edz250/3 ads# 12-19-14 tb1, tb2 12 green terminal block. onshore# edz250/2 ads# 12-19-13 tb3 51 inch center shunt berg# 65474-001 ads# 11-2-38 j1 to j5 5 male header. 1 inch center. berg #69157-102 ads# 11-2-37 j1 to j5 5 conn. bnc vert. mt telegartner # j01001a1944 ads# 12-6-22 s2 to s6 1 amp# 555154-1 mod. jack (shielded) 6 6 dek# a 9024 p1 1 3-pin gold male header waldom #wm 2723-nd dek# wm 2723-nd jp6 3 3-pin gold male locking header waldom #wm 2701-nd dek# wm 2701-nd p2 to p4 1 ad8016 arb ads# ad 8016 xrp dut 1 ad8016 soic rev. b evaluation pc board sierra/proto express eval pc board 4 no. 4 e40 1/4" panhead ss machine screw ads# 30-1-1 4 no. 4 e40 1/2" threaded alum. standoffs ads# 30-16-2 option 2 1:1.4 turns ratio rf transformer from coev c1374 rev. 2 t1, t2 24-lead batwing soic, thermally enhanced w/fused leads [soic/w/bat] (rb-24) dimensions shown in millimeters 0.33 0.20 1.27 0.40 8 0 0.75 0.25 45 24 13 12 1 15.60 15.20 7.60 7.40 pin 1 10.65 10.00 seating plane 0.30 0.10 0.51 0.31 2.65 2.35 1.27 bsc compliant with jedec standards ms-013ad outline dimensions
rev. b ad8016 e20e c01019e0e11/03(b) outline dimensions revision history location page 11/03?data sheet changed from rev. a to rev. b. changes to orderi ng gui de ...................................................................................................... ..............................................4 changes to tpc 21 .............................................................................................................. ...........................................................8 updated outline di mensi ons ..................................................................................................... ................................... 19-20 28-lead thin shrink small outline with exposed pad [tssop-ep] (re-28-1) dimensions shown in millimeters compliant to jedec standards mo-153aet 1.05 1.00 0.80 seating plane 1.20 max 0.15 0.00 0.30 0.19 4.50 4.40 4.30 28 15 14 1 9.80 9.70 9.60 pin 1 6.40 bsc 0.65 bsc 0.20 0.09 8 0 0.75 0.60 0.45 exposed pad (pins down) 3.00 bsc 3.50 bsc bottom view 20-lead power soic, thermally enhanced package [psop3] (rp-20a) dimensions shown in millimeters bottom view 6.20 5.80 13.00 9.00 8 0 2.90 max 2 places end view view a view a 1.10 0.80 seating plane 1.27 bsc 0.53 0.40 14.20 bsc 11.00 bsc 1 10 20 11 15.90 bsc top view 1.10 max 45 1.10 max 2 places pin 1 side view 3.60 3.35 3.10 1.00 0.90 0.80 3.60 3.35 3.10 3.30 3.15 3.00 0.30 0.20 0.10 0.10 0.05 0.00 0.32 0.23 compliant to jedec standards mo-166aa

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